There exists a PCM audio recorder as a device for recording and reproducing signals by conducting an A/D conversion by sampling analog signals at a sampling frequency Fs to obtain PCM data, constructing a frame by putting together a plurality of PCM data, and dividing (sharing) the same into a plurality of tracks. FIG. 1 shows a frame and a block construction of such a PCM recording apparatus, figure (a) shows a frame construction and figure (b) shows a block construction. One frame comprises 252 bits, and this comprises 14 samples of PCM data each quantized into 16 bits, 10 bits of a synchronous signal, 2 bits of a control signal, and 16 bits of C1 inspection data for error detection and correction. FIG. 1(b) shows a block construction in which frame constructed signals are recorded in a total of 8 tracks with 6 tracks for the PCM data and 2 tracks for the error detection correction data. The frame construction of FIG. 1 is determined in the following way.
Suppose that the number of channels of analog signals is N, the number of samples constituting one frame is S, and the number of tracks for recording the PCM data is Tr, the frame and block frequency F.sub.B is represented by the following formula. ##EQU1##
Supposing that the number of bits in one frame is T.sub.S, T.sub.S is represented by the following. EQU T.sub.S =B.times.S+m (4)
Herein, B is a quantization bit number of a sample (number of bits per sample), and m is a number of additional bits such as of a synchronous signal. The transmission frequency Fc for transmitting the bits in the frame is represented by the following formula. EQU F.sub.C =F.sub.B .times.T.sub.S ( 5)
Then, if the ratio of F.sub.C and F.sub.S .times.N becomes a simple integer, F.sub.C and F.sub.S .times.N can be generated from one clock, and the values of S and m are selected so as to enable the same. In the case of FIG. 1, N=2, S=14, Tr=6, and the block frequency F.sub.B becomes ##EQU2## when the F.sub.S is 48 kHz. Because the synchronous signal comprises 10 bits, the control signal comprises 2 bits, and C.sub.1 inspection data comprises 16 bits, the m=10+2+16=28. In addition, B=16, and thus T.sub.S =16.times.14+28=252 bits from the formula (4). Accordingly, from the formula (5) F.sub.C =252.times.1.143 kHz=288 kHz, and the ratio of F.sub.C and F.sub.S .times.N becomes a simple integer, that is, 288:48.times.2=3:1. Such a clock can be generated by the clock generator of FIG. 2.
In FIG. 2, the reference numeral 1 designates a master clock oscillator, the reference numeral 2 designates a .div.6 frequency divider, the reference numeral 3 designates a .div.42 frequency divider, the reference numeral 4 designates a 252 counter, and the reference numerals 5, 6, 7, and 8 are output terminals. A signal of 288 kHz is generated by the .div. master clock oscillator 1, and this signal is sent to the 6 frequency divider 2, the 252 counter 4, and the output terminal 6. The output of the .div.6 frequency divider 2 becomes 48 kHz, and this is sent to the .div.42 frequency divider 3 and the output terminal 8. The 252 counter 4 outputs clock signals required for such as the generation of the synchronous signal and the control signal to the output terminal 5. The .div.42 frequency divider 3 outputs clocks of block frequency F.sub.B to the output terminal 8.
FIG. 3 shows a block diagram of a PCM recording and reproducing apparatus which uses such a frame construction. In FIG. 3, the reference numeral 9 designates an input terminal for 2 channels of analog signals. The reference numeral 10 designates an A/D converter, the reference numeral 11 designates an encoder circuit, the reference numeral 12 designates a track sharing circuit, the reference numerals 13, 14, and 15 designate modulation circuits, the reference numerals 16, 17, and 18 designate recording amplifiers, the reference numerals 19, 20, and 21 designate recording heads, the reference numerals 22, 23, and 24 designate reproduction heads, the reference numerals 25, 26 and 27 designate reproduction amplifiers, the reference numerals 28, 29, and 30 designate demodulation circuits, the reference numerals 31, 32, and 33 designate time axis correction circuits (hereinafter referred to as "TBC circuit"), the reference numeral 34 designates a decoder circuit, the reference numeral 35 designates a D/A converter, the reference numeral 36 designates each channel analog output terminal, and the reference numeral 37 designates a clock generator.
The device operates as follows.
First of all, at the recording side, recording an analog signal input from the input terminal 9 is converted into PCM data having a quantization bit number B=16 by the A/D converter 10, and two error correction detection codes, that is, C.sub.2 inspection data and C.sub.1 inspection data are added thereto by the encoder circuit 11 so as to enable detecting and correcting errors due to limitations of the recording medium. A control signal is added to the encoded signal by the track sharing circuit 12, and the encoded signals split into 8 tracks to be sent to the modulation circuits 13, 14, and 15. These signals are modulated into signals appropriate for recording and reproducing on a recording medium by the modulation circuits 13, 14, and 15, a synchronous signal is added thereto, and this signal is recorded on a medium through the recording amplifiers 16, 17, and 18 and the recording heads 19, 20, and 21. At the reproduction side, the signals reproduced by the reproduction heads 22, 23, and 24 are amplified by the reproduction amplifiers 25, 26, and 27, the synchronous signals are detected and protected by the demodulation circuits 28, 29, and 30, the clocks are reproduced, and the clocks and the data from which the synchronous signals are separated are sent to the TBC circuits 31, 32, and 33. In the TBC circuits 31, 32, and 33 jitter and wow flutters are removed from the reproduced data, and the corrected data are sent to the decoder circuit 34. In the decoder circuit 34 error detection and correction of the data is conducted using the C.sub.1 inspection data and the C.sub.2 inspection data, the data is converted into the original analogue signal by the D/A converter 35, and it is output from the output terminal 36. Besides, the control signal is used for the control of the apparatus such as the control of the existence or non-existence of emphasis or the control of the frequency F.sub.S. The clock generator 37 is fundamentally constituted as shown in FIG. 2. A clock of frequency F.sub.S is sent to the A/D converter 10 and the D/A converter 35, and clocks of frequency F.sub.C and F.sub.B and the output of the output terminal 5 are sent to the track sharing circuit 12, the modulation circuits 13, 14, and 15, and the TBC circuits 31, 32, and 33.
In such a recording and reproducing apparatus a frame/block construction of FIG. 4 is utilized in a case where a second quantization bit number B.sub.2 =20 is used. Because there is only a difference in the quantization bit number relative to FIG. 1, T.sub.S becomes 20.times.14+28=308 from the formula (4), and F.sub.C becomes 1.143 kHz.times.308=352 WkHz from the formula (5). In this way, the bit number of one frame varies dependent on the quantization bit number such that 252 for a quantization bit numnber 16 and 308 for a quantization bit number 20. The main portion of a clock generator which corresponds to these two quantization bit numbers is shown in FIG. 5. In FIG. 5, the reference numeral 38 designates a master clock oscillator having a frequency of 3.168 MHz, the reference numeral 39 designates .div.11 frequency divider, the reference numeral 40 designates a .div.66 frequency divider, the reference numeral 41 designates a .div.9 frequency divider, the reference numeral 42 designates a 252 counter, the reference numeral 43 designates a .div.42 frequency divider, the reference numeral 44 designates a 308 counter, and the reference numerals 45, 46, 47, 48, 49, and 50 designate output terminals. When the quantization bit number is 16, the signals of the output terminals 45, 46, 47, and 48 are used as outputs, and when the quantization bit number is 20, the signals of the output terminals 47, 48, 49, and 50 are used as outputs.
The frame construction of the above-described PCM recording and reproducing apparatus has the following drawbacks.
First of all, as is apparent from FIGS. 2 and 5, the frequency of the master clock need become higher by eleven times as from 288 kHz to 3.168 MHz in order for the device to accommodate two quantization bit numbers, and this disadvantageously reduces the freedom of selection of clocks in a PCM recording and reproducing apparatus which uses various clocks for encoding. Further, the signals of the output terminals 45 to 50 are sent to the track sharing circuit 12 and the TBC circuits 31, 32, and 33, and if the bit number of one frame is changed, the control becomes complicated because these circuits usually use memories. Furthermore, when the bit number of one frame is changed the synchronous signal protection circuit in the decoder circuits 28, 29, and 30 does not operate, and the clocks to be sent to the TBC circuits 31, 32, and 33 must be switched for each track, thereby making the hardware complicated.